Stepping Through a Simulation - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
Release Date
2022.1 English

You can use the step command, which executes your HDL source code one line of source code at a time, to verify that the design is working as expected.

The line of code is highlighted and an arrow points to the currently executing line of code.

You can also create breakpoints for additional stops while stepping through your simulation. For more information on debugging strategies in the simulator, seethe section, Using Breakpoints, below.

  1. To step through a simulation:
    • From the current running time, select Run > Step, or click the Step button .

    The HDL associated with the top design unit opens as a new view in the Wave window.

    • From the start (0 ns), restart the simulation. Use the Restart command to reset time to the beginning of the test bench. See Simulating with Vivado Simulator.
  2. In the waveform configuration window, right-click the waveform or HDL tab and select Tile Horizontally see the waveform and the HDL code simultaneously.
  3. Repeat the Step action until debugging is complete.

As each line is executed, you can see the arrow moving down the code. If the simulator is executing lines in another file, the new file opens, and the arrow steps through the code. It is common in most simulations for multiple files to be opened when running the Step command. The Tcl Console also indicates how far along the HDL code the step command has progressed.