Targeting SystemVerilog for a Specific File - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English

By default, the Vivado IDE compiles .v files with the Verilog 2001 syntax and .sv files with the SystemVerilog syntax.

To target SystemVerilog for a specific .v file in the Vivado IDE:

  1. Right-click the file and select Set file type as shown in the figure below.

  2. In the Set Type dialog box, shown in the figure below, change the file type from Verilog to SystemVerilog and click OK.

Alternatively, you can use the following command in the Tcl Console:

set_property file_type SystemVerilog [get_files <filename>.v]