Functional simulation uses the UNISIM library and contains descriptions for device primitives or lowest-level building blocks.
compile_simlibcommand compiles the static simulation files for all the IP's in the IP Catalog.
Encrypted Component Files
The following table lists the UNISIM library component files that let you call precompiled, encrypted library files when you include IP in a design. Include the path you require in your library search path.
|<Vivado_Install_Dir>/data/verilog/src/unisim_retarget_comp.vp||Encrypted Verilog file|
|<Vivado_Install_Dir>/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhdp||Encrypted VHDL file|
VHDL UNISIM Library
The VHDL UNISIM library is divided into the following files, which specify the primitives for the Xilinx device families:
- The component declarations (
- Package files (unisim_VPKG.vhd)
To use these primitives, place the following two lines at the beginning of each file:
library UNISIM; use UNISIM.VCOMPONENTS.all;
Verilog UNISIM Library
In Verilog, the individual library modules are specified in separate
HDL files. This allows the
-y library specification
switch to search the specified directory for all components and automatically expand
The Verilog UNISIM library cannot be specified in the HDL file prior to using the module. To use the library module, specify the module name using all uppercase letters.
The following example shows the instantiated module name as well as the file name associated with that module:
- Module BUFG is BUFG.v
- Module IBUF is IBUF.v
Verilog is case-sensitive, ensure that UNISIM primitive instantiations adhere to an uppercase naming convention.
If you use precompiled libraries, use the correct simulator command-line switch to point to the precompiled libraries. The following is an example for the Vivado simulator:
-L is the library specification