For demo purpose, let us use the BFT example design shipped with Vivado IDE.
- Open the BFT example design in Vivado IDE.
launch_simulationwith Vivado as the selected simulator. You should see the ports shown in the following waveform.
- Select the desired scope for which you want to generate testbench as shown in
the following figure:
- Right-click the selected scope and select Generate VCD
- Delete all existing signals on the waveform and select Add to Wave
Window for the selected scope.Note: Step 5 will be used to demonstrate that the generated testbench is driving the design unit correctly.
close_vcd -portscommands on Tcl console to dump the signal activity. This logs the signal from time 0 to 2000 ns on the waveform as shown in the following figure:
create_testbench -name demo_tb -add_to_simset demo_simset -set_as_topcommand on Tcl console to generate testbench. This creates your testbench with the module name
demo_tband creates a
demo_simsetwith this testbench as top module.
launch_simulationcommand to run simulation with the newly generated testbench.
- Compare the input/output of the waveform with waveform of your original design, notice that the input/output are same.
This is how you can create testbench for your sub-design and use the generated testbench independently with any standard simulator.