Using Force Commands - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.1 English

The Vivado simulator provides an interactive mechanism to force a signal, wire, or register to a specified value at a specified time or period of time. You can also force values on objects to change over a period of time.

Tip: A 'force' is both an action (that is, the overriding of HDL-defined behavior on a signal) and also a Tcl first-class object, something you can hold in a Tcl variable.

You can use force commands on an HDL signal to override the behavior for that signal as defined in your HDL design. You might, for example, choose to override the behavior of a signal to:

  • Supply a stimulus to a test bench signal that the HDL test bench itself is not driving
  • Correct a bad value temporarily during debugging (allowing you to continue analyzing a problem)

The available force commands are:

  • Force Constant
  • Force Clock
  • Remove Force

The following figure illustrates how the add_force functionality is applied given the following command:

add_force mySig {0 t1} {1 t2} {0 t3} {1 t4} {0 t5} -repeat_every tr -cancel_after tc
Figure 1. Illustration of -add_force Functionality

You can get more detail on the command by typing the following in the Tcl Console:

add_force -help