You can use the simulation settings to specify the target simulator, display the simulation set, the simulation top module name, top module (design under test), tabbed listing of compilation, elaboration, simulation, netlist, and advanced options. From the Vivado IDE Flow Navigator, right-click Simulation and select Simulation Settings to open the Simulation Settings in the Settings dialog box, as shown in the following figure.
The Settings dialog box includes the following simulation settings:
- Target simulator
- From the simulator drop-down menu, select a simulator. Vivado® simulator is the default simulator. However, many third-party simulators are also supported.
- Simulator language
- Select the simulator language mode. The simulation model used for various IPs in your design varies depending on what language the IP supports.
- Simulation set
- Select the simulation set that the simulation commands use by default.Important: The compilation and simulation settings for a previously defined simulation set are not applied to a newly-defined simulation set.
- Simulation top module name
- Enter an alternate top module to use during simulation.
- Generate simulation scripts only
- Generates scripts if selected. Simulation is not invoked.
- Compiled library location
- This option is displayed when you select a third party simulator. This is a directory path for saving the compiled library results. By default, the libraries are saved in the current working directory in Non-Project mode. The libraries are saved in the <project>/<project>.cache/compile_simlib directory in project mode.
- Compilation tab
- This tab defines and manages compiler directives, which are stored as properties
on the simulation fileset and used by the xvlog and xvhdl utilities to compile
Verilog and VHDL source files for simulation.Note: xvlog and xvhdl are Vivado simulator specific commands. The applicable utilities will change based on the target simulator.
- Elaboration tab
- This tab defines and manages elaboration directives, which are stored as
properties on the simulation fileset and used by the xelab utility for
elaborating and generating a simulation snapshot. Select a property in the table
to display a description of the property and edit the value.Note: xelab is a Vivado simulator specific command. The applicable utilities will change based on the target simulator.
- Simulation tab
- This tab defines and manages simulation directives, which are stored as properties on the simulation fileset and used by the xsim application for simulating the current project. Select a property in the table to display a description of the property and edit the value.
- Netlist tab
- This tab provides access to netlist configuration options related to SDF annotation of the Verilog netlist and the process corner captured by SDF delays. These options are stored as properties on the simulation fileset and are used while writing the netlist for simulation.
- Advanced tab
- This tab contains two options:
- Enable incremental compilation
- This option enables the incremental compilation and preserves the simulation files during successive run.
CAUTION:Changing the settings in the Advanced tab should be done only if necessary. The Include all design sources for simulation check box is selected by default. Deselecting the box could produce unexpected results. As long as the check box is selected, the simulation set includes Out-of-Context (OOC) IP, IP Integrator files, and DCP.Note: For detailed information on the properties in the Compilation, Elaboration, Simulation, Netlist, and Advanced tabs, see Compilation, Elaboration, Simulation, Netlist, and Advanced Options.
- Include all design sources for simulation
- By default, this option is enabled. Selecting this option ensures that all the files from design sources along with the files from the current simulation set will be used for simulation. Even if you change the design sources, the same changes will be updated when you launch behavioral simulation.