The ASYNC_REG constraint:
- Identifies asynchronous registers in the design
- Disables X propagation for those registers
The ASYNC_REG constraint can be attached to a register in the front-end design by using either:
- An attribute in the HDL code
- A constraint in the Xilinx Design Constraints (XDC)
The registers to which
ASYNC_REG are attached retain the previous value during timing simulation, and do not output an X to simulation. Use care; a new value might have been clocked in as well.
The ASYNC_REG constraint is applicable to CLB and Input Output Block (IOB) registers and latches only. For more information, see ASYNC_REG constraint at this link in the Vivado Design Suite Properties Reference Guide (UG912).
If you cannot avoid clocking in asynchronous data, do so for IOB or CLB registers only. Clocking in asynchronous signals to RAM, Shift Register LUT (SRL), or other synchronous elements has less deterministic results; therefore, should be avoided. Xilinx highly recommends that you first properly synchronize any asynchronous signal in a register, latch, or FIFO before writing to a RAM, Shift Register LUT (SRL), or any other synchronous element. For more information, see the Vivado Design Suite User Guide: Using Constraints (UG903).