VHDL Instantiation Unit - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English

When a VHDL design instantiates a component, the xelab command treats the component name as a VHDL unit and searches for it in the logical work library.

  • If a VHDL unit is found, the xelab command binds it and the search stops.
  • If xelab does not find a VHDL unit, it treats the case-preserved component name as a Verilog module name and continues a case-sensitive search in the user-specified list and order of unified logical libraries. The command selects the first matching the name, then stops the search.
  • If case sensitive search is not successful, xelab performs a case-insensitive search for a Verilog module in the user-specified list and order of unified logical libraries. If a unique binding is found for any one library, the search stops.