ASYNC_REG VHDL Examples - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

attribute ASYNC_REG : string;

attribute ASYNC_REG of sync_regs : signal is "TRUE";

attribute ASYNC_REG : boolean;

attribute ASYNC_REG of sync_regs : signal is TRUE;