Behavioral Data Types Example - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

This coding example shows sample Verilog data types found in the declaration section of a Verilog module.

wire net1; // single bit net

reg r1; // single bit register

tri [7:0] bus1; // 8 bit tristate bus

reg [15:0] bus1; // 15 bit register

reg [7:0] mem[0:127]; // 8x128 memory register

parameter state1 = 3'b001; // 3 bit constant

parameter component = "TMS380C16"; // string