Behavioral Verilog Generate Case Statements Coding Example - 2022.1 English

This coding example instantiates more than two different implementations of an adder based on the width of data words.

generate

case (WIDTH)

1:

   begin : case1_name

adder #(WIDTH*8) x1 (a, b, ci, sum_case, c0_case);

   end

2:

   begin : case2_name

adder #(WIDTH*4) x2 (a, b, ci, sum_case, c0_case);

    end default:

begin : d_case_name

adder x3 (a, b, ci, sum_case, c0_case);

end

endcase

endgenerate