Behavioral Verilog Module Instantiation Example - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

module top (A, B, C, O); input  A, B, C; output O;

   wire  tmp;

 

   example inst_example (.A(A), .B(B), .O(tmp));

 

   assign O = tmp | C;

 

endmodule