Block-Level Flow Options - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

The block-level flow supports some of the predefined strategies that are in the tool as well. The strategies that are allowed are: DEFAULT, AREA_OPTIMIZED, ALTERNATE_ROUTABILITY, and PERFORMANCE_OPTIMIZED. The XDC constraint syntax is as follows:

set_property BLOCK_SYNTH.STRATEGY {<value>} [get_cells <inst_name>]

The following table lists the supported Vivado Block synthesis settings.

Table 3-1:      BLOCK_SYNTH Supported Settings

Option

Type

Values

Description

RETIMING

INTEGER

0/1

0 – Disable Retiming

1 – Enable Retiming

ADDER_THRESHOLD

INTEGER

4-128

Changes the threshold for the size of an adder for synthesis to infer in a CARRY chain.

Higher numbers mean more LUTs.

Lower numbers mean more CARRY chains.

The threshold is calculated by adding the sizes of the adder operands. The specified value should be >= sum of the input widths.

COMPARATOR_THRESHOLD

INTEGER

4-128

Changes the threshold for the size of a comparator for synthesis to infer in a CARRY chain.

Higher numbers mean more LUTs.

Lower numbers mean more CARRY chains.

SHREG_MIN_SIZE

INTEGER

3-32

Changes the threshold for the size of a register chain before synthesis will infer SRL primitives.

Higher numbers mean more registers.

Lower numbers mean more SRLs.

FSM_EXTRACTION

STRING

OFF

ONE_HOT

SEQUENTIAL

GRAY

JOHNSON

AUTO

Sets the encodings of state machines that the synthesis tool infers.

LUT_COMBINING

INTEGER

0/1

0 – Disable LUT combining

1 – Enable LUT combining

CONTROL_SET_THRESHOLD

INTEGER

0-128

Controls the fanout needed on control signals before synthesis infers registers with control signals.

Higher numbers mean less logic on control signals and more on D input of flop.

Lower numbers mean more control signals and less logic on D input.

MAX_LUT_INPUT

INTEGER

4-6

4 – No LUT5 or LUT6 primitives will be inferred

5 – No LUT6 primitives will be inferred

6 – All LUTs can be inferred.

MUXF_MAPPING

INTEGER

0/1

0 – Disable MUXF7/F8/F9 inference

1 – Enable MUXF7/F8/F9 inference

KEEP_EQUIVALENT_REGISTER

INTEGER

0/1

0 – Merges equivalent registers

1 – Retains equivalent registers

PRESERVE_BOUNDARY

INTEGER

Any number

This option can be used with incremental synthesis. It is used to mark hierarchies that are known to change. Using this option can make the hierarchy static and allow the incremental flow to work. The value given does not matter because just having this option set is sufficient.

LOGIC_COMPACTION

INTEGER

1

Arranges CARRY chains and LUTs in such a way that it makes the logic more compact using fewer SLICES.

SRL_STYLE

STRING

REGISTER

SRL

SRL_REG

REG_SRL

REG_SRL_REG

Sets the default implementation for inferred SRLs.