CLOCK_BUFFER_TYPE VHDL Example - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

entity test is port(

   in1 : std_logic_vector (8 downto 0);

   clk : std_logic;

   out1 : std_logic_vector(8 downto 0));

   attribute clock_buffer_type : string;

   attribute clock_buffer_type of clk: signal is "BUFR";

end test;