Code Example (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Load the data as follows:

type RamType is array(0 to 7) of bit_vector(31 downto 0);

impure function InitRamFromFile (RamFileName : in string) return RamType is

FILE RamFile : text is in RamFileName;

variable RamFileLine : line;

variable RAM : RamType;

begin

for I in RamType'range loop

readline (RamFile, RamFileLine);

read (RamFileLine, RAM(I));

end loop;

return RAM;

end function;

signal RAM : RamType := InitRamFromFile("rams_20c.data");