•Do not asynchronously set or reset registers.
°Control set remapping becomes impossible.
°Sequential functionality in device resources such as block RAM components and DSP blocks can be set or reset synchronously only.
°If you use asynchronously set or reset registers, you cannot leverage device resources, or those resources are configured sub-optimally.
•Do not describe flip-flops with both a set and a reset.
°No Flip-flop primitives feature both a set and a reset, whether synchronous or asynchronous.
°Flip-flop primitives featuring both a set and a reset may adversely affect area and performance.
•Avoid operational set/reset logic whenever possible. There may be other, less expensive, ways to achieve the desired effect, such as taking advantage of the circuit global reset by defining an initial content.
•Always describe the clock enable, set, and reset control inputs of flip-flop primitives as active-High. If they are described as active-Low, the resulting inverter logic will penalize circuit performance.