Compilation Units - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

System Verilog supports both single file and multiple file compilation through use of Compilation units.

A compilation unit is a collection of one or more SV source files compiled together. Every compilation unit is associated with single library. The “compilation unit scope” is a scope that is local to a global compilation unit, the scope has all the declarations that lie outside of any other design scope. Generally functions, tasks, parameter, nets, variables and user defined types declared outside the module, interface, package or program come under the compilation unit scope.

For example, consider the following design.

In TCL mode

    read_verilog -lib lib1 { }

    read_verilog -lib lib2 { }





In the above case if has declarations in the compilation unit scope such as params, typedefs etc, like

Parameter P1 =2;   // Parameter declared out of module scope

             Module test1 (<port list>)




and read the files as mentioned above. Compiler unit scope starts with reading file under lib1, but while reading with lib2 would be illegal because compilation unit should be associated with single library. This can be addressed by following ways:

In TCL mode, putting all the files in a single library.

             read_verilog -lib lib1 {}

             read_verilog -lib lib1 {}


or not declaring libraries at all

             read_verilog { }

             read_verilog  {}




or (single file compilation unit mode)

                        read_verilog -lib lib1 {}

                        read_verilog -lib lib2 {}


                        synth_design -top <top_name> -sfcu