Complex Multiplier Examples - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

The following examples show complex multiplier examples in VHDL and Verilog. Note that the coding example files also include a complex multiplier with accumulation example that uses three DSP blocks for the UltraScale™ architecture.