The Vivado IDE supports designating one of more Verilog or Verilog Header source files as global ‘include files and processes those files before any other sources. Designs that use common header files might require multiple `include statements to be repeated across multiple Verilog sources used in the design.
To designate a Verilog or Verilog header file as a global `include file:
1.In the Sources window, select the file.
2.Check the Global include check box in the Source File Properties window, as shown in This Figure.
TIP: In Verilog, reference header files that are specifically applied to a single Verilog source (for example; a particular `define macro), with an `include statement instead of marking it as a global `include file.