Dual-Port RAM with Asynchronous Read Coding Example (Verilog) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Filename: rams_dist.v

 

 

 

// Dual-Port RAM with Asynchronous Read (Distributed RAM)

// File: rams_dist.v

 

module rams_dist (clk, we, a, dpra, di, spo, dpo);

 

input clk;

input we;

input [5:0] a;

input [5:0] dpra;

input [15:0] di;

output [15:0] spo;

output [15:0] dpo;

reg [15:0] ram [63:0];

 

always @(posedge clk)

begin

if (we)

  ram[a] <= di;

end

 

assign spo = ram[a];

assign dpo = ram[dpra];

 

endmodule