Example of if-else Statement (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

library IEEE;

use IEEE.std_logic_1164.all;


entity mux4 is port (

   a, b, c, d : in std_logic_vector (7 downto 0);

   sel1, sel2 : in std_logic;

   outmux : out std_logic_vector (7 downto 0));

end mux4;


architecture behavior of mux4 is begin

   process (a, b, c, d, sel1, sel2)


      if (sel1 = '1') then

      if (sel2 = '1') then

      outmux <= a;


   else outmux <= b;


   end if;

      if (sel2 = '1') then outmux <= c;


      outmux <= d;

   end if;

end if;

   end process;

end behavior;