VHDL-2008 allows the use of functions and assignments within the port map of an instantiation. One useful way this is used is in converting signals from one type to another, as shown in the following example:
U0 : my_entity port map (clk => clk, in1 => to_integer(my_signal)...
In the case above, the entity, my_entity had a port called in1 that was of type integer, but in the upper-level, the signal, my_signal was of type std_logic_vector.
Previously in VHDL, you would have to create a new signal of type integer and do the conversion outside of the instantiation, and then assign that new signal to the port map.
In addition to type conversion, you can put logic into the port map, as shown in the following example:
U0 : my_entity port map (clk => clk, enable => en1 and en2 ...
In this case the lower-level has an enable signal. On the top-level that enable is tied to the AND of two other signals.
Previously in VHDL, this, like the previous example would have needed a new signal and assignment, but in VHDL-2008 can be accomplished in the port map of the instantiation.