FULL_CASE Example (Verilog) - 2022.1 English
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English
(* full_case *)
case select
3’b100 : sig = val1;
3’b010 : sig = val2;
3’b001 : sig = val3;
endcase