In VHDL-2008, you can declare undefined functions inside of entities. For example
entity bottom is
generic (
function my_func (a,b : unsigned) return unsigned);
port ...
......
end entity bottom;
Then later in the architecture of the entity:
process(clk) is
begin
if rising_edge(clk) then
y <= my_func(a,b);
end if;
end process;
This uses the my_func function, inside of the entity, but it still has not defined what this function actually accomplishes. That is defined when bottom is instantiated in an upper level RTL.
inst_bot1 : bottom
generic map (
my_func => my_func1 )
port map ...
So this ties the function my_func1 that was declared in a VHDL file or a package file to the generic function my_func. As long as my_func1 has two inputs called a and b that are both unsigned, it will be able to work.