Generic Types in Entities - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
Release Date
2022.1 English

VHDL-2008 supports undefined types in the generic statement for an entity. For example:

entity my_entity is

    generic (type my_type);


    port (in1 : in std_logic;

          out1 : out my_type);

end entity my_entity;

This would declare an entity with an undetermined type and then the RTL that instantiates my_entity would look like:

my_inst1 : entity work.my_entity(beh) generic map (my_type => std_logic) port map ...

my_inst2 : entity work.my_entity(beh) generic map (my_type => std_logic_vector(3 downto 0)) port map ...

The code above instantiates my_entity twice, but in once case out1 will be a bit and in the other case out1 will be a 4 bit vector.