The Vivado Synthesis tool can do many types of memories using the UltraRAM primitives.
For examples, see the Coding Guidelines.
•In single port memory, the same port that reads the memory also writes to it. All three of the write modes for the block RAM are supported, but it should be noted that the UltraRAM itself acts like a NO_CHANGE memory. If WRITE_FIRST or READ_FIRST behavior is described in the RTL, then the UltraRAM created will be set in simple dual port mode.
•In a simple dual port memory, one port reads from the RAM while the other port writes to it. Vivado synthesis can infer these memories into UltraRAM.
TIP: One stipulation is that both ports must have the same clock.
•In True Dual Port mode, both ports can read from and write to the memory. In this mode, only the NO_CHANGE mode is supported.
CAUTION! Care should also be taken when simulating the true dual port RAM. In the previous versions of block RAM, there was address collision that was taken care of by the simulation models; with the UltraRAM it is different. In the UltraRAM, port A will always happen before port B. If Port A has a write and Port B is a read from that address, the memory is written to and then read from, but if Port A has the read and port B has the write, the old value is seen during the read.
CAUTION! Be sure to never read and write to the same address during the same clock cycle on a true dual port memory because the RTL and post-synthesis simulations could be different.
For both the simple dual port memory and the true dual port memory, the clocks have to be the same for both ports.
In addition to the different styles of RAMs, there are also a few other features of the UltraRAM that can be inferred. The RAM has a global enable signal that takes precedence over the write enable. It has the standard write enable and byte write enable support. The data output also has a reset like the previous block RAM; however, in this case there is no SRVAL that can be set, only resets of 0 are supported.