Instantiating Pre-Defined Primitives - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

The structural features of Verilog allow you to design circuits by instantiating pre-defined primitives such as: gates, registers, and Xilinx-specific primitives such as CLKDLL and BUFG.

These primitives are additional to those included in Verilog, and are supplied with the Xilinx® Verilog libraries (unisim_comp.v).