Instantiating an FDC and a BUFG Primitive Example - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

The unisim_comp.v library file includes the definitions for FDC and BUFG.

module example (sysclk, in, reset, out);

input sysclk, in, reset;

output out;

reg out;

wire sysclk_out;


FDC register (out, sysclk_out, reset, in); //position based referencing

BUFG clk (.O(sysclk_out),.I(sysclk)); //name based referencing