KEEP Example (Verilog) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

(* keep = "true" *) wire sig1;

assign sig1 = in1 & in2;

assign out1 = sig1 & in2;