MAX_FANOUT Example (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

signal sig1 : std_logic;

attribute max_fanout : integer;

attribute max_fanout of sig1 : signal is 50;

Note:   In VHDL, max_fanout is an integer.