Module Declaration - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

A Behavioral Verilog module declaration consists of:

°The module name

°A list of circuit I/O ports

°The module body in which you define the intended functionality

End with an endmodule statement.