SystemVerilog has two types of timing controls:
•Delay control: Specifies the amount of time between the statement its execution. This is not useful for synthesis, and Vivado synthesis ignores the time statement while still creating logic for the assignment.
•Event control: Makes the assignment occur with a specific event; for example, always@(posedge clk). This is standard with Verilog, but SystemVerilog includes extra functions.
The logical or operator is an ability to give any number of events so that any event triggers the execution of the statement. To do this, use either a specific or, or separate with commas in the sensitivity list. For example, the following two statements are the same:
always@(a or b or c)
SystemVerilog also supports the implicit event_expression @*. This helps to eliminate simulation mismatches caused because of incorrect sensitivity lists.
Logic always@* begin