After you create the lower-level netlist and instantiate the top-level netlists correctly, you can either add the lower-level netlists to the Vivado project in Project mode, or you can use the read_edif or read_verilog command in Non-Project mode.
In both modes, the Vivado tool merges the netlist after synthesis.
Note: If a design is from third-party netlists only, and no other RTL files are meant to be part of the project, you can either create a project with just those netlists, or you can use the read_edif and read_verilog Tcl commands along with the link_design Tcl command in Non-Project Mode.