RW_ADDR_COLLISION - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

The RW_ADDR_COLLISION attribute is for specific types of RAMs. When a RAM is a simple dual port and the read address is registered, Vivado synthesis will infer a block RAM and set the write mode to WRITE_FIRST for best timing. Also, if a design writes to the same address that it is reading from, the output of the RAM is unpredictable. RW_ADDR_COLLISION overrides this behavior.

The values for RW_ADDR_COLLISION are:

"auto": Default behavior as described above.

"yes": This inserts bypass logic so that when an address is read from the same time it is written to, the value of the input will be seen on the output making the whole array behave as WRITE_FIRST.

"no": This is when the user does not care about timing or the collision possibility. In this case the write mode will be set to NO_CHANGE resulting in a power savings.

RW_ADDR_COLLISION is supported in RTL only.