Reading Output Ports - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

In previous versions of VHDL, it was illegal to use signals declared as out for anything other than an output.

So if you wanted to assign a value to an output, and also use that same signal for other logic, you would either have to declare a new signal and have that drive the output and the other logic, or switch from an out to a buffer type.

VHDL-2008 lets you use output values, as shown in the following example:

entity test is port(

in1 : in std_logic;

clk : in std_logic;

out1, out2 : out std_logic);

end test;

And then later in the architecture:

process(clk) begin

if clk’event an clk=’1’ then

   out1 <= in1;

   my_reg <= out1;  -- THIS WOULD HAVE BEEN ILLEGAL in VHDL.

   out2 <= my_reg;

end if;

end process;