Sequential Assignments - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

VHDL-2008 allows sequential signal and variable assignment with conditional signals. For example, a register with an enable would be written as the following:

process(clk) begin

   if clk’event and clk=’1’ then

      if enable then

         my_reg <= my_input;

      end if;

   end if;

end process;

With VHDL-2008, this can now be written as the following:

process(clk) begin

    if clk’event and clk=’1’ then

         my_reg <= my_input when enable else my_reg;

    end if;

end process;