Vivado synthesis allows two input types: RTL source code and timing constraints. To add RTL or constraint files to the run:
1.From the File menu or the Flow Navigator, select the Add Sources command to open the Add Sources wizard, shown in the following figure.
2.Select an option corresponding to the files to add, and click Next.
The following figure shows the Add or Create Design Sources page that is displayed if Add or create design sources is selected.
3.Add constraint, RTL, or other project files, then click Finish.
See this link to the Vivado Design Suite User Guide: System-Level Design Entry (UG895) [Ref 8] for more information about creating RTL source projects.
The Vivado synthesis tool reads the subset of files that can be synthesized in VHDL, Verilog, SystemVerilog, or mixed language options supported in the Xilinx tools.
The following chapters provide details on supported HDL constructs.
Vivado synthesis also supports several RTL attributes that control synthesis behavior. Synthesis Attributes, describes these attributes. For timing constraints, Vivado synthesis uses the XDC file.
Using Block Synthesis Strategies describes the available Block Synthesis Strategies.
IMPORTANT: Vivado Design Suite does not support the UCF format. See this link in the ISE to Vivado Design Suite Migration Guide (UG911) [Ref 18] for the UCF to XDC conversion procedure.