Structural Verilog descriptions assemble several blocks of code and allow the introduction of hierarchy in a design. The following table lists the concepts of hardware structure and their descriptions.
|
Concept |
Description |
|---|---|
|
Component |
Building or basic block |
|
Port |
Component I/O connector |
|
Signal |
Corresponds to a wire between components |
The following table lists the Verilog Components, the view, and what the components describe.
|
Item |
View |
Describes |
|---|---|---|
|
Declaration |
External |
What is seen from the outside, including the component ports |
|
Body |
Internal |
The behavior or the structure of the component |
•A component is represented by a design module.
•The connections between components are specified within component instantiation statements.
•A component instantiation statement:
°Specifies an instance of a component occurring within another component or the circuit
°Is labeled with an identifier.
°Names a component declared in a local component declaration.
°Contains an association list (the parenthesized list). The list specifies the signals and ports associated with a given local port.