Tristate Description Using Concurrent Assignment Coding Example (Verilog) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Filename: tristates_2.v

 

 

 

// Tristate Description Using Concurrent Assignment

// File: tristates_2.v

//

module tristates_2 (T, I, O);

input  T, I;

output O;

 

assign O = (~T) ? I: 1'bZ;

 

endmodule