Xilinx IP that is available in the Vivado IP Catalog is designed, constrained, and validated with the Vivado Design Suite synthesis.
Note: Even though this is a synthesis setting, -mode out_of_context will not trigger a full resynthesis.
Most Xilinx-delivered IP has HDL that is encrypted with IEEE P1735, and no support is available for third-party synthesis tools for Xilinx IP.
To instantiate Xilinx IP that is delivered with the Vivado IDE inside of a third-party synthesis tool, the following flow is recommended:
1.Create the IP customization in a managed IP project.
2.Generate the output products for the IP including the synthesis design checkpoint (DCP).
The Vivado IDE creates a stub HDL file, which is used in third-party synthesis tools to infer a black box for the IP (_stub.v | _stub.vhd). The stub file contains directives to prevent I/O buffers from being inferred; you might need to modify these files to support other synthesis tool directives.
3.Synthesize the design with the stub files for the Xilinx IP.
4.Use the netlist produced by the third-party synthesis tool, and the DCP files for the Xilinx IP, then run Vivado implementation. For more information, see this link to the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9].