In VHDL, when listing items in the sensitivity list of a process statement for combinational logic, it was up to the designer to make sure all the items read by the process statement were listed. If any were missed, there would be Warning messages and possible latches inferred in the design.
With VHDL-2008, you can use the process(all) statement that looks for all the inputs to the process and then creates the logic.
process(all) begin
enable <= en1 and en2;
end process;