VHDL GENERICs have the following properties:
•Are equivalent to Verilog parameters.
•Help you create scalable design modelizations.
•Let you write compact, factorized VHDL code.
•Let you parameterize functionality such as bus size, and the number of repetitive elements in the design unit.
For the same functionality that must be instantiated multiple times, but with different bus sizes, you need describe only one design unit with generics. See the GENERIC Parameters Example.