Complex circuits are often designed using a top-down methodology.
•Varying specification levels are required at each stage of the design process. For example, at the architectural level, a specification can correspond to a block diagram or an Algorithmic State Machine (ASM) chart.
•A block or ASM stage corresponds to a register transfer block in which the connections are N-bit wires, such as:
°Finite State Machine (FSM)
•Verilog allows the expression of notations such as ASM charts and circuit diagrams in a computer language.