Verilog Instance Example - 2022.1 English
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English
(* DONT_TOUCH = "yes" *) example_dt_ver U0
(.clk(clk),
.in1(a),
.in2(b),
out1(c));