Automatically derived clocks are also called auto-generated clocks. The Vivado IDE automatically creates the constraint for these on the output pins of the Clock Modifying Blocks (CMBs), provided the associated master clock has already been defined.
In the Xilinx 7 series device family, the CMBs are:
- MMCM*/ PLL*
In the Xilinx UltraScale™ device family, the CMBs are:
- MMCM* / PLL*
- BUFG_GT / BUFGCE_DIV
- GT*_COMMON / GT*_CHANNEL / IBUFDS_GTE3
- BITSLICE_CONTROL / RX*_BITSLICE
An auto-generated clock is not created if a user-defined clock (primary or generated) is also defined on the same netlist object, that is, on the same definition point (net or pin). The auto-derived clock is named with the segment name in the top-most hierarchy of the net that is connected to the definition point.