After propagating on the board and inside the FPGA, the clock edges arrive at their destination with a certain delay. This delay is typically represented by:
- The source latency (delay before the clock source point, usually, outside the device)
- The network latency
The delay introduced by the network latency (also called insertion delay) is either automatically estimated (pre-route design) or accurately computed (post-route design).
Many non-Xilinx timing engines require the SDC command
set_propagated_clock to trigger the computation of propagation
delay along the clock trees. The Vivado tool does not require this
command. Instead, it computes the clock propagation delay by default:
- All clocks are considered propagated clocks.
- A generated clock latency includes the insertion delay of its master clock plus its own network latency.
For Xilinx FPGAs, use the
primarily to specify the clock latency outside the device.
# Minimum source latency value for clock sysClk (for both Slow and Fast corners) set_clock_latency -source -early 0.2 [get_clocks sysClk] # Maximum source latency value for clock sysClk (for both Slow and Fast corners) set_clock_latency -source -late 0.5 [get_clocks sysClk]