The set_max_delay command can also be used to constrain asynchronous
signals that do not have a clock relationship, but which require maximum delay.
For example, timing paths between two asynchronous clock domains can be disabled with the
set_clock_groups command (recommended) or the
set_false_path command (not recommended). This assumes that you
have properly designed the inter-clock domains with, for instance, a double registers
synchronizer or a FIFO. However, you must still ensure that the path delay between the
two clock domains is not unnecessarily high.
In some multi-bit CDC scenarios the skew between the bits must be within certain
requirements. Even though the skew can be constrained through the Bus Skew constraint
(set_bus_skew), it must be ensured that the path
delay between the two clock domains is not unnecessarily high. This can be done by
replacing the set_false_path or set_clock_groups constraints inside the source XDC file on the relevant
path(s) with set_max_delay –datapath_only. Refer to
CDC Constraints for further information on constraining CDC
paths.
If a maximum delay must be specified for some or for all the paths between two clock
domains, then you must use the command set_max_delay -datapath_only to
constrain those paths. In this case, set_clock_groups cannot be used to
define the two clock domains as asynchronous, as it supersedes the
set_max_delay constraint in terms of constraint priority. Other
cross clock domains paths must then be constrained with a combination of
set_false_path or set_max_delay constraints.
See the following example:
set_max_delay <delay> -datapath_only -from <startpoints_source_clock_domain> \
-to <endpoints_destination_clock_domain>