The dedicated hardware resources of Xilinx FPGAs efficiently support a large number of design clocks. These clocks are usually generated by an external component on the board. They usually enter the device through an input port.
They can also be generated by special primitives called Clock Modifying Blocks, such as:
They can also be transformed by regular cells such as LUTs and registers.
The following sections describe how to best define clocks based on where they originate.