set_input_delay command specifies the input path delay on an input
port relative to a clock edge at the interface of the design.
When considering the application board, the input delay represents the phase difference between:
- The data propagating from an external chip through the board to an input package pin of the FPGA, and
- The relative reference board clock.
Consequently, the input delay value can be positive or negative, depending on the clock and data relative phase at the interface of the device.