The Timing Constraints wizard analyzes all paths from input ports to identify their destination clock inside the design and their active edges. Based on this information, the wizard recommends basic system synchronous input delay constraints that are based on the XDC templates available in the Vivado IDE (see XDC Templates for templates). The waveform associated with the selected template is displayed at the bottom of the window in the Waveform tab when you select a constraint entry in the Recommended Constraints table.
The following figure shows an example of several input constraints proposed by the wizard and partially edited by the user.
For each constraint, you can edit three characteristics in order to specify the appropriate waveform that corresponds to the actual interface timing on the board:
- Describes the nature of the clock-data relationship.
- System (for System Synchronous interface)
- Use this setting when the data is launched and captured by different clock edges that are 1 period or ½ period apart.
- Source (for Source Synchronous interface)
- Use this setting when the data is launched and captured by the same clock edge.
- Describes the data transition alignment with respect to the active clock
- For System Synchronous interfaces only:
- Use this setting when the clock and data transition at the same time.
- For Source Synchronous interfaces only:
- Use this setting when the clock transitions in the middle of the data valid window.
- Edge Direct
- Use this setting when the clock transitions at the beginning of the data valid window.
- Edge MMCM
- Use this setting when the clock transitions at the end of the data valid window.
- For System Synchronous interfaces only:
- Data Rate and Edge
- Describes the active clock edges constrained by the template. The default value
recommended by the wizard is based on the active clock edges of the capturing
- Single Rise
- Use this setting for cases where only the rising clock edges launch the data outside the FPGA.
- Single Fall
- Use this setting for cases where only the falling clock edges launch the data outside the FPGA.
- Use this setting for cases where both rising and falling clock edges launch the data outside the FPGA.
The recommended clock is usually the board clock related to the input path sequential cell. When the input path internal clock is an MMCM or PLL generated clock, the board clock that drives the MMCM or PLL is used as the input constraint reference clock. The only exceptions exist when the internal clock waveform and the board clock waveform are not identical, such as the following scenarios:
- Different period scenario
- The input constraint references a virtual clock that has the same waveform as the internal clock so that the setup analysis is performed with a 1 cycle path requirement. The virtual clock is automatically created.
- Positive phase-shift clock scenario
- The wizard uses a virtual clock as the reference clock. The virtual clock is
automatically created with the same waveform as the board clock. In addition,
the wizard also specifies a multicycle path constraint between the virtual clock
and the internal clock to adjust the default analysis to 1 period + the amount
of phase-shift for setup. The combination of the virtual clock and the
multicycle path constraint provides simpler constraints for the Vivado Design Suite timer to handle and can only affect input ports
that reference to the virtual clock.
Note that for a negative phase-shift, the virtual clock and the multicycle path constraint are not needed because the default setup path requirement is 1-cycle minus the amount of phase-shift.
The wizard does not allow you to change the reference clock selected for the constraint. To do so, you must manually edit the XDC files or use the Timing Constraints window after exiting the wizard.
After you select the proper template, enter the delay parameter values in the Delay Parameters panel located on the right hand side of the wizard and then click Apply to validate the entries.
The input delay equations are displayed below the delay parameter fields and on some of the template waveforms. The following figure shows the Delay Parameters panel for the DDR System Synchronous interface template.
To accelerate the delay parameter entry task, you can select and edit several constraints with same clock and same template at once.
After the constraints have been completed and applied, you can review their corresponding Tcl syntax in the Tcl Command Preview tab or you can click Next to proceed to the next step.